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Declarative Symbolic Pure-Logic Model Checking (2005)
| Content Provider | CiteSeerX |
|---|---|
| Researcher | Shlyakhter, Ilya A. |
| Abstract | Model checking, a technique for findings errors in systems, involves building a formal model that describes possible system behaviors and correctness conditions, and using a tool to search for model behaviors violating correctness properties. Existing model checkers are well-suited for analyzing control-intensive algorithms (e.g. network protocols with simple node state). Many important analyses, however, fall outside the capabilities of existing model checkers. Examples include checking algorithms with complex state, distributed algorithms over all network topologies, and highly declarative models. This thesis addresses |
| File Format | |
| Publisher Date | 2005-01-01 |
| Access Restriction | Open |
| Subject Keyword | Possible System Behavior Control-intensive Algorithm Correctness Property Finding Error Complex State Declarative Model Simple Node State Declarative Symbolic Pure-logic Model Checking Many Important Analysis Correctness Condition Model Behavior |
| Content Type | Text |
| Resource Type | Thesis |
