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EDF-DVS Scheduling on the IBM Embedded PowerPC 405LP (2004)
| Content Provider | CiteSeerX |
|---|---|
| Author | Ali, Aravindh Anantaraman Mahmoud, Ali El-Haj Venkatesan, Ravi K. Zhu, Yifan Mueller, Frank |
| Description | Power consumption has become a major concern, both for processor design with high clock rates and embedded systems that rely on batteries to operate. Recent support for dynamic frequency and voltage scaling (DVS) in contemporary architectures allows software to affect power consumption by varying both execution frequency and supply voltage on the fly. However, processors generally enter a sleep state while transitioning between frequencies/voltages. In the following, we describe an experimental framework for studying DVS for a processor that continues to execute during frequency/voltage transitions. For this purpose, we developed an infrastructure for investigating hard real-time DVS schemes on the IBM PowerPC 405LP. Task scheduling was performed using four earliest-deadline-first (EDF) DVS schemes, including our feedback real-time DVS algorithm that, prior to this work, had only been evaluated in simulation. Voltage and current of the processor core were depicted through an oscilloscope, and the energy consumption was assessed through a data acquisition board. Measurements indicate a considerable potential for real-time DVS scheduling algorithms to lower energy consumption up to 54% over na ve DVS schemes. The benefits of continued execution during frequency/voltage switching provide up to 5% energy savings for frequent switches. |
| File Format | |
| Language | English |
| Publisher Date | 2004-01-01 |
| Publisher Institution | In Proceedings of the IBM Pa=c 2 Conference |
| Access Restriction | Open |
| Subject Keyword | Recent Support Hard Real-time Dvs Scheme Dvs Scheme Energy Consumption Considerable Potential Processor Core Energy Saving Ibm Embedded Powerpc Real-time Dvs Feedback Real-time Dvs Algorithm Dynamic Frequency Task Scheduling Supply Voltage Voltage Scaling Sleep State Frequency Voltage Transition Na Ve Dvs Scheme Execution Frequency Frequency Voltage Major Concern Data Acquisition Board Frequent Switch Continued Execution Processor Design Contemporary Architecture High Clock Rate Ibm Powerpc Power Consumption Experimental Framework |
| Content Type | Text |
| Resource Type | Article |
