Loading...
Please wait, while we are loading the content...
Similar Documents
Self-checking carry-select adder with sum-bit duplication.
| Content Provider | CiteSeerX |
|---|---|
| Author | Sogomonyan, E. S. Marienfeld, D. Ocheretnij, V. Gössel, M. |
| Abstract | Abstract: In this paper the first code-disjoint totally self-checking carry-select adder is proposed. The adder blocks are fast ripple adders with a single NAND-gate delay for carry-propagation per cell. In every adder block both the sum-bits and the corre-sponding inverted sum-bits are simultaneously implemented. The parity of the input operands is checked against the XOR-sum of the propagate signals. For 64 bits area and maximal delay are determined by the SYNOPSYS CAD tool of the EUROCHIP project. Compared to a 64 bit carry-select adder without error detection the delay of the most significant sum-bit does not increase. Compared to a completely duplicated code-disjoint carry-select adder we save 240 XOR-gates. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Self-checking Carry-select Adder Sum-bit Duplication Adder Block Single Nand-gate Delay Bit Carry-select Adder Maximal Delay First Code-disjoint Synopsys Cad Tool Code-disjoint Carry-select Adder Bit Area Fast Ripple Adder Propagate Signal Corre-sponding Inverted Sum-bits Significant Sum-bit Eurochip Project Error Detection |
| Content Type | Text |
| Resource Type | Article |
