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Improving Cache Locality for Thread-Level Speculation Systems (2005)
| Content Provider | CiteSeerX |
|---|---|
| Author | Fung, Stanley Lap Chiu Lap, Stanley Fung, Chiu |
| Description | In IPDPS 20 With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the performance of an individual program. However, with such speculatively-parallel execution the cache locality once enjoyed by the original uniprocessor execution is significantly disrupted: for TLS execution on a four-processor CMP, we find that the data-cache miss rates are nearly four-times those of the uniprocessor case, even though TLS execution utilizes four private data caches. |
| File Format | |
| Language | English |
| Publisher Date | 2005-01-01 |
| Access Restriction | Open |
| Subject Keyword | Promising Technique Uniprocessor Case Thread-level Speculation System Four-processor Cmp Data-cache Miss Rate Tl Execution Individual Program Thread-level Speculation Speculatively-parallel Execution Original Uniprocessor Execution Cache Locality Private Data Cache |
| Content Type | Text |
| Resource Type | Article |
