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Gate Delay Fault Test Generation for Non-Scan Circuits
| Content Provider | CiteSeerX |
|---|---|
| Abstract | This article presents a technique for the extension of delay fault test pattern generation to synchronous sequential circuits without making use of scan techniques. The technique relies on the coupling of TDgen, a robust combinational test pattern genera tor for delay faults, and SEMILET, a sequential test pattern generator for several static fault models. The approach uses a forward propagation- backward justlfication technique: The test pattern generation is started at the fault location, and after successful "local " test generation faull effect propagation is performed and finally a synchronising sequence to the required state is computed. The algorithm is complete for a robust gate delay fault model, which means that for every testable fault a test will be generated, assuming suflcient time. Experimental results for the ISCAS'89 benchmarks are presented in this paper. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Technique Relies Sequential Test Pattern Generator Fault Location Robust Gate Delay Fault Model Gate Delay Fault Test Generation Forward Propagation Backward Justlfication Technique Non-scan Circuit Testable Fault Several Static Fault Model Scan Technique Synchronising Sequence Delay Fault Test Pattern Generation Suflcient Time Synchronous Sequential Circuit Delay Fault Required State Test Pattern Generation |
| Content Type | Text |
| Resource Type | Article |
