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Minimum delay adder for redundant complex binary number system.
| Content Provider | CiteSeerX |
|---|---|
| Author | Saleem, Jawad Ali, Usman Saeed, Sadaf Khan, Shahid A. |
| Abstract | Abstract: We find the applications of complex numbers in almost all fields of modern science and engineering. Due to its much application a lot of research work is underway to reduce the computation requirements for the Complex binary numbers. Recent research indicates that complex numbers can be represented in single binary-unit format as in Complex Binary Number System (CBNS) with bases (−1+j) and (−1−j). One-unit binary representation of complex numbers in CBNS form reduces computational complexity in arithmetic operations involving such numbers, although the problem of carry appears to be more pronounced in this system compared to base-2 binary system. This has led to the definition of Redundant Complex Binary Number System (RCBNS), which permits carry-free addition of complex binary numbers. This paper proposes an hardware architecture for the carry-free addition of RCBNS. The presented adder is developed directly from truth table of 3-bit block RCBNS addition. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Redundant Complex Binary Number System Complex Number Minimum Delay Adder Complex Binary Number Carry-free Addition Cbns Form Computational Complexity Truth Table Presented Adder Single Binary-unit Format Modern Science Recent Research Much Application Complex Binary Number System Research Work Base-2 Binary System Hardware Architecture Arithmetic Operation 3-bit Block Rcbns Addition One-unit Binary Representation Computation Requirement |
| Content Type | Text |
| Resource Type | Article |
