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A low-power SRAM using bitline charge-recycling (2008)
| Content Provider | CiteSeerX |
|---|---|
| Author | Kim, Keejong Mahmoodi, Hamid Roy, Kaushik |
| Abstract | We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance. In order to improve the data retention capability of un-selected cells during write, the power supply lines of memory cells in one column are connected to each other and separated from the power lines of other columns. A test-chip is fabricated in 0.13μm CMOS and measurement results show 88 % reduction in total power compared to the conventional SRAM (CON-SRAM) at VDD=1.5V and f=100MHz. |
| File Format | |
| Journal | IEEE J. Solid-State Circuits |
| Language | English |
| Publisher Date | 2008-01-01 |
| Access Restriction | Open |
| Subject Keyword | Bitline Charge-recycling Low-power Sram Memory Cell Adjacent Bit-line Capacitance Write Scheme Write Operation Conventional Sram New Low-power Sram Total Power Power Supply Line Recycled Charge Differential Voltage Swing Bit-line Charge Recycling Un-selected Cell Measurement Result Power Line Data Retention Capability |
| Content Type | Text |
| Resource Type | Article |
