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A Parallel Hierarchical Algorithm For Module Placement Based On Sparse Linear Equations (1996)
Content Provider | CiteSeerX |
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Author | Xing, Zhaoyun Banerjee, Prithviraj St, W. Main |
Description | We present a fast and effective module placement algorithm which is based on the PROUD algorithm. The PROUD algorithm uses a hierarchical decomposition technique and the solution of sparse linear systems of equations based on a resistive network analogy. It has been shown that the PROUD algorithm is suitable for solving the placement problem for very large circuits, and obtains placement qualities that are comparable to the best placement algorithms based on simulated annealing, but is several orders of magnitude faster. In this paper, we first report on an improved hierarchical placement algorithm which is based on perturbing the matrices in the matrix equation solution stage of the PROUD algorithm. The new modified PROUD algorithm performs much faster that the original PROUD algorithm. We subsequently propose parallel versions of the original and modified algorithms that combine both fine grain and coarse grain parallelism to obtain another order of magnitude improvement in the runti... |
File Format | |
Language | English |
Publisher Date | 1996-01-01 |
Publisher Institution | In Proceedings of the 1996 International Conference on Circuits and Systems |
Access Restriction | Open |
Subject Keyword | Modified Algorithm Module Placement Parallel Version Simulated Annealing Resistive Network Analogy Hierarchical Decomposition Technique Magnitude Improvement Placement Quality Sparse Linear System New Modified Proud Algorithm Performs Several Order Fine Grain Large Circuit Sparse Linear Equation Coarse Grain Parallelism Original Proud Algorithm Matrix Equation Solution Stage Magnitude Faster Effective Module Placement Algorithm Placement Problem Proud Algorithm Parallel Hierarchical Algorithm Placement Algorithm Improved Hierarchical Placement Algorithm |
Content Type | Text |
Resource Type | Article |