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High-performance scheduling algorithm for partially parallel ldpc decoder.
| Content Provider | CiteSeerX |
|---|---|
| Author | Zhan, Cheng-Zhou Shih, Xin-Yu Wu, An-Yeu Andy |
| Abstract | In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partially parallel LDPC architecture is commonly used for reducing the area cost of the processing units. The dependency of two kinds of processing units, check node unit (CNU) and bit node unit (BNU), should be considered to enhance the hardware utilization efficiency (HUE). Based on the properties of the parity check matrix of LDPC codes, the updating calculation of the CNU and BNU can be overlapped to reduce the decoding latency by enhancing the HUE with the matrix scheduling algorithm. By applying our proposed LDPC scheduling algorithm to a (1944, 972)-irregular LDPC code, we can get about 60 % throughput gain in average without any performance degradation. Index Terms — LDPC, scheduling, overlapped, matrix, |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Node Unit General Low-density Parity Check Hardware Utilization Efficiency Irregular Ldpc Code Index Term Ldpc Overlapped Message Updating Calculation Area Cost New Scheduling Algorithm Parity Check Matrix Throughput Gain Decoding Latency Ldpc Code Performance Degradation Parallel Ldpc Architecture |
| Content Type | Text |
