Loading...
Please wait, while we are loading the content...
Similar Documents
The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays.
| Content Provider | CiteSeerX |
|---|---|
| Author | Chen, Ping Ye, Andy |
| Abstract | The increased use of multi-bit processing elements such as digital signal processors, multipliers, multi-bit addressable memory cells, and CPU cores has presented new opportunities for Field-Programmable Gate Array (FPGA) architects to utilize the regularity of multi-bit signals to increase the area efficiency of FPGAs. In particular, configuration memory sharing has been traditionally used to exploit multi-bit regularity for area. We observe that the process of creating configuration memory sharing routing resources often leads to the use of much sparser switch patterns for connecting multi-bit elements to their routing tracks. In this work, we empirically evaluate the effect of these sparse switch patterns on the area efficiency of FPGAs. It is shown that the sparse switch patterns alone contribute significantly to the area reduction observed in configuration memory sharing FPGAs. In particular, our experiments show that, without configuration memory sharing, sparse switch patterns can reduce the implementation area of multi-bit routing resources by 10.4 % while configuration memory sharing contributes to an additional 1.2 % in area savings. The observation holds over a wide range of connection block flexibility values and demonstrates that efficient switch pattern designs can be effectively used to increase the area efficiency of FPGA routing resources. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Configuration Memory Area Efficiency Configuration Memory Sharing Sparse Switch Pattern Area Reduction Wide Range Multi-bit Processing Element Area Saving Implementation Area Cpu Core Multi-bit Routing Resource Field-programmable Gate Array Digital Signal Processor Sparse Switch Much Sparser Switch Pattern Multi-bit Signal Multi-bit Element Efficient Switch Pattern Design Routing Resource Routing Track Multi-bit Addressable Memory Cell Multi-bit Regularity New Opportunity Connection Block Flexibility Value |
| Content Type | Text |
