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Race analysis for systemc using model checking
| Content Provider | CiteSeerX |
|---|---|
| Author | Kroening, Daniel Blanc, Nicolas |
| Abstract | Abstract—SystemC is a system-level modeling language that offers a wide range of features to describe concurrent systems at different levels of abstraction. The SystemC standard permits simulators to implement a deterministic scheduling policy, which often hides concurrency-related design flaws. We present a novel compiler for SystemC that integrates a formal and scalable race analysis. This analysis combines both classic static analysis and Model Checking techniques. The outcome of the analysis is not only valuable to diagnose the effect of race conditions, but can also be used to improve simulation performance dramatically. Our compiler produces a simulator that uses the race analy-sis information at runtime to perform partial-order reduction, thereby eliminating context switches that do not affect the result of the simulation. Experimental results show simulation speedups of one order of magnitude and better. I. |
| File Format | |
| Journal | ACM Trans. Des. Autom, Electron. Syst |
| Access Restriction | Open |
| Subject Keyword | Race Analy-sis Information Simulation Performance Race Analysis Scalable Race Analysis Novel Compiler Concurrency-related Design Flaw Context Switch Systemc Standard Race Condition Classic Static Analysis Simulation Speedup Partial-order Reduction Abstract Systemc Deterministic Scheduling Policy System-level Modeling Language Model Checking Technique |
| Content Type | Text |
