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Ulsi interconnect length distribution model considering core utilization.
| Content Provider | CiteSeerX |
|---|---|
| Author | Nakashima, Hidenari Inoue, Junpei Okada, Kenichi Masu, Kazuya |
| Abstract | Interconnect Length Distribution (ILD) represents a cor-relation between the number of interconnects and length. The ILD can predict power consumption, clock frequency, chip size, etc. It has been said that high core utilization and small circuit area improve chip performance. We propose a ILD model to predict a correlation between core utilization and chip performance. The proposed model predicts influences of interconnect length and interconnect density on circuit performances. As core utilization in-creases, small and simple circuits improve the perform-ances. In large complex circuits, decrease of load capaci-tance is more important than that of total interconnect length for improvement of chip performance. The proposed ILD model expresses actual ILD more accurate than con-ventional models. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Chip Performance Ild Model Large Complex Circuit Core Utilization In-creases Interconnect Density Interconnect Length Distribution High Core Utilization Load Capaci-tance Interconnect Length Power Consumption Con-ventional Model Total Interconnect Length Circuit Performance Actual Ild Clock Frequency Chip Size Small Circuit Area Core Utilization Simple Circuit |
| Content Type | Text |
