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Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers (1990)
| Content Provider | CiteSeerX |
|---|---|
| Author | Jouppi, Norman P. |
| Abstract | Projections of computer technology forecast proces-sors with peak performance of 1,000 MIPS in the rela-tively near future. These processors could easily lose half or more of their performance in the memory hierar-chy if the hierarchy design is based on conventional caching techniques. This paper presents hardware tech-niques to improve the performance of caches. Miss caching places a small fully-associative cache between a cache and its refill path. Misses in the cache that hit in the miss cache have only a one cycle miss penalty, as o posed to a many cycle miss penalty without the miss cacke. Small miss caches of 2 to 5 entries are shown to be very effective in removing mapping conflict misses in first-level direct-mapped caches. Victim caching is an improvement to miss caching that loads the small fully-associative cache with the vic-tim of a miss and not the requested line. Small victim caches of 1 to 5 entries are even more effective at remov-ing conflict misses than miss caching. refetch cache lines starting at a cache miss address. $he prefetched data is placed in the buffer and not in the cache. Stream buffers are useful in removing capacity and compulsory cache misses, as well as some instruction cache conflict misses. Stream buf-fers are more effective than previously investigated prefetch techni ues at using the next slower level in the memory hierarAy when it is pipelined. An extension to the basic stream buffer, called multi-way stream buffers, is introduced. Multi-way stream buffers are useful for prefetching along multiple intertwined data reference streams. Together, victim caches and stream buffers reduce the miss rate of the first level in the cache hierarchy by a factor of two to three on a set of s1x large benchmarks. |
| File Format | |
| Publisher Date | 1990-01-01 |
| Access Restriction | Open |
| Subject Keyword | Victim Caching Prefetch Buffer Miss Rate S1x Large Benchmark First Level Stream Buffer Basic Stream Buffer Cycle Miss Penalty Instruction Cache Conflict Miss Multi-way Stream Buffer Miss Cacke Remov-ing Conflict Miss Computer Technology Cache Line Miss Caching Victim Cache Compulsory Cache Miss Mapping Conflict Miss Memory Hierar-chy Refill Path Direct-mapped Cache Performance Small Victim Cache Cache Miss Address First-level Direct-mapped Cache Prefetch Techni Ues Memory Hieraray Requested Line Miss Cache Cache Hierarchy Stream Buf-fers Data Reference Stream Hardware Tech-niques Small Miss Cache Hierarchy Design Many Cycle Peak Performance Small Fully-associative Cache |
| Content Type | Text |
| Resource Type | Article |
