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Towards an ultra-low-power architecture using single-electron tunneling transistors.
| Content Provider | CiteSeerX |
|---|---|
| Author | Zhu, Changyun Guy, Zhenyu Peter Shang, Li Dicky, Robert P. Knobelz, Robert G. |
| Abstract | Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultra-low-power designs may even permit embedded systems to operate without batteries, e.g., by scavenging energy from the environment. Moreover, managing power dissipation is now a key factor in integrated circuit packaging and cooling. As a result, embedded system price, size, weight, and reliability are all strongly dependent on power dissipation. Recent developments in nanoscale devices open new alternatives for low-power embedded system design. Among these, single-electron tunneling transistors (SETs) hold the promise of achieving the lowest power consumption. However, SETs impose unique design constraints that strongly influence architectural and circuit-level decisions. Unfor-tunately, most analysis of SETs has focused on single devices instead of architectures, making it difficult to determine whether they are appropriate for low-power embedded systems. This article presents possible uses of SETs in high-performance and battery-powered embedded system design. The resulting fault-tolerant, hybrid SET/CMOS, reconfigurable architecture can be tailored to specific requirements and allows trade-offs among power consumption, performance, operation temperature, fabrication cost, and reliability. This work is a first step in evaluating the system-level potential of reducing power consumption by using SETs. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Power Consumption Single-electron Tunneling Transistor Ultra-low-power Architecture Power Dissipation Circuit-level Decision System-level Potential Embedded System Design Fabrication Cost Reconfigurable Architecture Operation Temperature Battery-powered Embedded System Design Integrated Circuit Packaging Nanoscale Device Open New Alternative Unique Design Constraint Hybrid Set Cmos Specific Requirement Possible Us Single Device System Price Key Factor Ultra-low-power Design Low-power Embedded System Design First Step Recent Development |
| Content Type | Text |
| Resource Type | Article |
