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Temperature-sensitive loop parallelization for chip multiprocessors (2005)
| Content Provider | CiteSeerX |
|---|---|
| Author | Hari, Sri Narayanan, Krishna Chen, Guilin Mahmut, K. Xie, Yuan |
| Description | In Proceedings of the International Conference on Computer Design In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multipro-cessors in order to reduce the peak temperature. Our experimental results show that the peak (average) tem-perature can be reduced by 20.9◦C (4.3◦C) when av-eraged over all the applications tested, incurring small performance/power penalties. 1 |
| File Format | |
| Language | English |
| Publisher Date | 2005-01-01 |
| Access Restriction | Open |
| Subject Keyword | Chip Multiprocessor Chip Multipro-cessors Small Performance Power Penalty Temperature-sensitive Loop Parallelization Experimental Result Array-intensive Application Temperature-sensitive Loop Parallelization Strategy Peak Temperature |
| Content Type | Text |
| Resource Type | Article |
