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Heads and tails: a variable-length instruction format supporting parallel fetch and decode (2001)
| Content Provider | CiteSeerX |
|---|---|
| Author | Pan, Heidi |
| Description | In Proc. of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems |
| Abstract | Abstract. Existing variable-length instruction formats pro-vide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and decode. This paper presents a new variable-length instruction format that supports parallel fetch and decode of multiple instruc-tions per cycle, allowing both high code density and rapid exe-cution for high-performance embedded processors. In contrast to earlier schemes that store compressed variable-length in-structions in main memory then expand them into fixed-length in-cache formats, the new format is suitable for direct execu-tion from the instruction cache, thereby increasing effective cache capacity and reducing cache power. The new head-and-tails (HAT) format splits each instruction into a fixed-length head and a variable-length tail, and packs heads and tails in separate sections within a larger fixed-length instruction bun-dle. The heads can be easily fetched and decoded in parallel as they are a fixed distance apart in the instruction stream, while the variable-length tails provide improved code density. A conventional MIPS RISC instruction set is re-encoded in a variable-length HAT scheme, and achieves an average static code compression ratio of 75 % and a dynamic fetch ratio (new-bits-fetched/old-bits-fetched) of 75%. 1 |
| File Format | |
| Publisher Date | 2001-01-01 |
| Access Restriction | Open |
| Subject Keyword | Variable-length Tail New Variable-length Instruction Format Instruction Stream Compressed Variable-length In-structions Average Static Code Compression Ratio Fixed-length Instruction Bun-dle Variable-length Instruction Format Effective Cache Capacity Separate Section New Head-and-tails Cache Power High Code Density Fixed Distance Parallel Fetch Dynamic Fetch Ratio Conventional Mips Risc Instruction Set Direct Execu-tion Main Memory Fixed-length Format Instruction Fetch Rapid Exe-cution Multiple Instruc-tions Fixed-length Head New Format Variable-length Hat Scheme Fixed-length In-cache Format Code Density High-performance Embedded Processor Instruction Cache Pack Head |
| Content Type | Text |
| Resource Type | Conference Proceedings Article |
