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Retrospective: using cache memory to reduce processor-memory traffic.
| Content Provider | CiteSeerX |
|---|---|
| Author | Goodman, James R. |
| Abstract | vv hile it has long been recognized that memory latency was a key parameter of perfor-mance, the impact of memory bandwidth (or its absence) has always been much harder to charac-terize. The complex relationship between latency and bandwidth is much better understood today than it was in 1982. Nevertheless, this relationship in the ever-varying context of “modern ” system designs, created a fertile ground for studying a range of solutions to the same problem over many generations of computers: how to balance band-width and latency to provide a cost-effective, high-performance memory system [1,3]. This paper was an enthusiastic attempt by an assistant professor- who had never had a paper |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Using Cache Memory Processor-memory Traffic Memory Bandwidth High-performance Memory System Memory Latency Complex Relationship Many Generation Assistant Professor Fertile Ground Vv Hile Understood Today Key Parameter Ever-varying Context Modern System Design Enthusiastic Attempt |
| Content Type | Text |
| Resource Type | Article |
