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Automatic Intra-Register Vectorization for the Intel Architecture (2002)
| Content Provider | CiteSeerX |
|---|---|
| Author | Bik, Aart J. C. Girkar, Milind Grey, Paul M. Tian, Xinmin |
| Abstract | Recent extensions to the Intel ® Architecture feature the SIMD technique to enhance the performance of computational intensive applications that perform the same operation on different elements in a data set. To date, much of the code that exploits these extensions has been hand-coded. The task of the programmer is substantially simplified, however, if a compiler does this exploi-tation automatically. The high-performance Intel ® C++/Fortran compiler supports automatic translation of serial loops into code that uses the SIMD extensions to the Intel ® Architecture. This paper provides a detailed overview of the automatic vectorization methods used by this compiler together with an experimental validation of their effectiveness. KEY WORDS: Compilers; instruction-level-parallelism; SIMD; vectorization. 1. |
| File Format | |
| Journal | International Journal of Parallel Programming |
| Language | English |
| Publisher Date | 2002-01-01 |
| Access Restriction | Open |
| Subject Keyword | Intel Architecture Automatic Intra-register Vectorization High-performance Intel Fortran Compiler Automatic Translation Experimental Validation Serial Loop Key Word Data Set Detailed Overview Different Element Automatic Vectorization Method Simd Extension Simd Technique Recent Extension Computational Intensive Application |
| Content Type | Text |
| Resource Type | Article |
