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Post-verification debugging of hierarchical designs.
| Content Provider | CiteSeerX |
|---|---|
| Author | Fahim, Moayad Sean, Ali Andreas, Safarpour Magdy, Veneris Abadir, S. Drechsler, Rolf |
| Abstract | As VLSI designs grow in complexity and size, errors become more frequent and difficult to track. Recent developments have automated most of the verification tasks but debugging still remains a resource-intensive, manually conducted procedure. This paper bridges this gap as it develops robust automated debugging methodologies that complement verification processes. Unlike prior debugging tech-niques, the proposed one exploits the hierarchical nature of modern designs to improve the performance and quality of debugging. It also formulates the problem in terms of Quantified Boolean For-mula Satisfiability to obtain dramatic reduction in memory require-ments which allows for debugging of large designs. Extensive ex-periments conducted on industrial and benchmark designs confirm the efficiency and practicality of the proposed approach. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Hierarchical Design Post-verification Debugging Verification Task Dramatic Reduction Large Design Recent Development Extensive Ex-periments Benchmark Design Verification Process Hierarchical Nature Modern Design Quantified Boolean For-mula Satisfiability Memory Require-ments Conducted Procedure |
| Content Type | Text |
| Resource Type | Article |
