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Low-power techniques for network security processors ∗.
| Content Provider | CiteSeerX |
|---|---|
| Author | You, Yi-Ping Tseng, Chun-Yen Huang, Yu-Hui Huang, Po-Chiun Hwang, Tingting Hsu, Sheng-Yu |
| Abstract | Abstract — In this paper, we present several techniques for low-power design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual thresh-old voltage assignments, for network security processors. The ex-periments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Network Security Processor Low Power Present Several Technique Dual Thresh-old Voltage Assignment High Performance Descriptor-based Low-power Scheduling Algorithm Dynamic Voltage Generator |
| Content Type | Text |
