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Ocp tlm for architectural modeling.
| Content Provider | CiteSeerX |
|---|---|
| Author | Kogel, Tim |
| Abstract | Over the last years Transaction Level Modeling has established itself as a valuable strategy to solve system-level design problems prior to the implementation phase. The System-Level Design Working Group of the OCP-IP consortium has contributed SystemC TLM channel packages and methodology guidelines to help the proliferation of this modeling paradigm since 2002 [6]. Meanwhile, SystemC in general and TLM in particular have been improved and standardized by Open SystemC Initiative [1], [2], [3]. The predominant use models for SystemC based Transaction Level Modeling (TLM) are the highly abstract Programmers View (PV) [7], [8] as well as fully cycle-accurate modeling for verification and HDL co-simulation. However, so far no methodology for abstract performance modeling has been established addressing HW/SW partitioning and architectural exploration. We propose an Architects View (AV) TLM use-case, which is based on revised OCP Transaction Level 2 (TL2) and TL3 APIs. The goal is to allow SoC architects to identify and resolve bottlenecks in the organizations of the SW and HW architectures. Problems to be solved are e.g. the number of processors required, how different pieces of SW and algorithms will access main |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Architectural Modeling Ocp Tlm Last Year Transaction Level Modeling Hw Sw Partitioning Systemc Tlm Channel Package Predominant Use Model Modeling Paradigm Different Piece Revised Ocp Transaction Level Methodology Guideline Tlm Use-case System-level Design Problem Cycle-accurate Modeling Soc Architect Valuable Strategy Architect View Implementation Phase Abstract Performance Modeling Architectural Exploration Hw Architecture Transaction Level Modeling Abstract Programmer View Open Systemc Initiative System-level Design Working Group Tl3 Apis Hdl Co-simulation Ocp-ip Consortium |
| Content Type | Text |
