High Performance Dividers with Multiply-Add (1996)

Content Provider	CiteSeerX
Author	Phillips, J. E. Vassiliadis, S.
Description	This study describes a new technique, based on quadratic convergence, to implement a divider using multiply-add operations. The end result is improved execution time for the division, when compared to traditional dividers and previously proposed quadratic convergence algorithms. In addition, while improving delay, no extra hardware is needed to implement the algorithm. On the contrary, less overhead hardware is required when compared to previously proposed schemes, assuming the hardware of the multiply-add is needed anyway to perform multiplication and multiply-add instructions. 1. Introduction The division operation has been implemented mostly in the past using algorithms that produce the quotient via successive additions/subtractions [3]. Such a family of algorithms produces slow division implementations or prohibitive hardware when a faster divider is desired. A divide algorithm based on quadratic convergence was originally designed for the IBM System 360 Model 91 [1] that when ap... In 2nd International Conference on Massively Parallel Computing Systems
File Format	PDF
Language	English
Publisher Date	1996-01-01
Access Restriction	Open
Subject Keyword	End Result Extra Hardware Multiply-add Operation Quadratic Convergence Algorithm Multiply-add Instruction Execution Time Divide Algorithm Prohibitive Hardware High Performance Divider Overhead Hardware Ibm System Division Operation Traditional Divider New Technique Algorithm Produce Slow Division Implementation Successive Addition Subtraction Quadratic Convergence
Content Type	Text
Resource Type	Article