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Early Periodic Register Allocation on ILP Processors (2004)
| Content Provider | CiteSeerX |
|---|---|
| Author | Touati, Sid-Ahmed-Ali |
| Abstract | Register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation as a rst step without assuming a schedule lacks the information of interferences between values live ranges. Thus, the register allocator may introduce an excessive amount of false dependences that dramatically reduce the ILP (Instruction Level Parallelism). We present a new theoretical framework for controlling the register pressure before software pipelining. This is based on inserting some anti-dependence edges (register reuse edges) labeled with reuse distances, directly on the data dependence graph. In this new graph, we are able to x the register pressure, measured as the number of simultaneously alive variables in any schedule. The determination of register and distance reuse is parameterized by the desired minimum initiation interval (MII) as well as by the register pressure constraints- either can be minimized while the other one is xed. After scheduling, register allocation is done on conventional register sets or on rotating register les. We give an optimal exact model, and an approximation that generalizes the Ning-Gao [22] buffer optimization method. We provide experimental results which show good improvement compared to [22]. Our theoretical model considers superscalar, VLIW and EPIC/IA64 processors. |
| File Format | |
| Publisher Date | 2004-01-01 |
| Access Restriction | Open |
| Subject Keyword | Distance Reuse Excessive Amount Anti-dependence Edge Jean-luc Gaudiot Register Allocation Desired Minimum Initiation Interval Conventional Register Set Software Pipelining Rst Step Epic Ia64 Processor Register Le Theoretical Model Considers Data Dependence Graph Register Allocator Optimal Exact Model Reuse Distance Register Pressure Constraint New Graph Register Allocation Alive Variable Conventional Register Allocation False Dependence Register Pressure Instruction Level Parallelism Experimental Result Good Improvement New Theoretical Framework Buffer Optimization Method Register Reuse Edge |
| Content Type | Text |
