NDLI: Enabling a uniform programming model across the software/hardware boundary. Fccm’06 (2006).

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Enabling a uniform programming model across the software/hardware boundary. Fccm’06 (2006).

Content Provider	CiteSeerX
Author	Anderson, Erik Agron, Jason Peck, Wesley Stevens, Jim Baijot, Fabrice Sass, Ron Andrews, David
Abstract	In this paper, we present hthreads, a unifying pro-gramming model for specifying application threads running within a hybrid CPU/FPGA system. Threads are speci-fied from a single pthreads multithreaded application pro-gram and compiled to run on the CPU or synthesized to run on the FPGA. The hthreads system, in general, is unique within the reconfigurable computing community as it ab-stracts the CPU/FPGA components into a unified custom threaded multiprocessor architecture platform. To support the abstraction of the CPU/FPGA component boundary, we have created the hardware thread interface (HWTI) compo-nent that frees the designer from having to specify and em-bed platform specific instructions to form customized hard-ware/software interactions. Instead, the hardware thread interface supports the generalized pthreads API semantics, and allows passing of abstract data types between hard-ware and software threads. Thus the hardware thread in-terface provides an abstract, platform independent compi-lation target that enables thread and instruction-level par-allelism across the software/hardware boundary. 1
File Format	PDF
Publisher Date	2006-01-01
Access Restriction	Open
Subject Keyword	Uniform Programming Model Software Hardware Boundary Hardware Thread Interface Abstract Data Type Software Thread Hthreads System Multiprocessor Architecture Platform Single Pthreads Application Pro-gram Independent Compi-lation Target Cpu Fpga Component Software Hardware Customized Hard-ware Software Interaction Em-bed Platform Specific Instruction Hybrid Cpu Fpga System Application Thread Unifying Pro-gramming Model Hardware Thread In-terface Generalized Pthreads Api Semantics Unified Custom Instruction-level Par-allelism Cpu Fpga Component Boundary
Content Type	Text

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