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A low-voltage high-speed cmos inverter-based digital differential transmitter with impedance matching control and mismatch calibration.
| Content Provider | CiteSeerX |
|---|---|
| Author | Bae, Jun-Hyun Park, Sang-Hune Sim, Jae-Yoon Park, Hong-June |
| Abstract | Abstract—A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a 0.18 μm CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a 0.18 μm CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4 Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200 % and the timing margin by |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Impedance Matching Control Mismatch Calibration Supply Voltage Cmos Process Data Rate Pvt Variation Standard Supply Voltage Falling-edge Delay Output Impedance Pre-driver Output Transmission Line Timing Margin Digital Differential Transmitter Transmitter Output Cmos Inverter Calibration Scheme Rising-edge Delay Voltage Margin |
| Content Type | Text |
