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A Comparison of Superscalar and Decoupled Access/Execute Architectures (1993)
| Content Provider | CiteSeerX |
|---|---|
| Author | Farrens, Matthew Nico, Phil Ng, Pius |
| Description | In Proceedings of the 26th Annual ACM/IEEE International Symposium on Microarchitecture |
| Abstract | This paper presents a comparison of superscalar and decoupled access/execute architectures. Both architectures attempt to exploit instruction-level parallelism by issuing multiple instructions per cycle, employing dynamic scheduling to maximize performance. Simulation results are presented for four different configurations, demonstrating that the architectural queues of the decoupled machines provide similar functionality to register renaming, dynamic loop unrolling, and out-of-order execution of the superscalar machines with significantly less complexity. 1. Introduction The importance of being able to make use of the available parallelism in a task is becoming more and more clear. Research over the last 30 years has demonstrated the difficulty of writing parallel programs; however, there are a number of techniques for exploiting instructionlevel parallelism that have been proposed. The most commercially successful approach has been superscalar architectures [John91], which execute ... |
| File Format | |
| Publisher Date | 1993-01-01 |
| Access Restriction | Open |
| Subject Keyword | Decoupled Machine Similar Functionality Multiple Instruction Different Configuration Successful Approach Out-of-order Execution Decoupled Access Execute Architecture Dynamic Loop Unrolling Instructionlevel Parallelism Simulation Result Architectural Queue Instruction-level Parallelism Dynamic Scheduling Available Parallelism Superscalar Machine Superscalar Architecture Parallel Program |
| Content Type | Text |
| Resource Type | Proceeding Conference Proceedings Article |
