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Exploiting sub-word parallelism for dependable processors toshinori sato.
| Content Provider | CiteSeerX |
|---|---|
| Abstract | Abstract:- This paper presents an approach for integrating fault-tolerance techniques into microprocessors by exploiting sub-word parallelism. Smaller transistors, higher clock frequency, and lower power supply voltage reduce reliability of microprocessors. In addition, they are used in systems which require high dependability, such as e-commerce businesses. Based on the trends, it is expected that the quality with respect to reliability will become important for future microprocessors. To meet the demand, we have proposed and evaluated a fault-tolerance mechanism, which is based on instruction reissue and utilizes time redundancy, and found severe performance loss. In order to mitigate the loss, this paper proposes to exploit sub-word parallelism. Redundant instructions are executed in parallel in the form of a SIMD instruction. Detailed simulations show that the performance loss in 4-way and 8-way superscalar processors is reduced to only 25.0 % and 15.8%, respectively. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Sub-word Parallelism Dependable Processor Toshinori Sato E-commerce Business Utilizes Time Redundancy Power Supply Voltage Instruction Reissue Detailed Simulation Smaller Transistor Fault-tolerance Mechanism Future Microprocessor Clock Frequency Severe Performance Loss Performance Loss Fault-tolerance Technique Redundant Instruction Simd Instruction 8-way Superscalar Processor High Dependability |
| Content Type | Text |
| Resource Type | Article |
