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Mixed-mode timing simulation for accurate cmos bridging fault detection.
| Content Provider | CiteSeerX |
|---|---|
| Author | Tian, Yanmei Hajj, Ibrahim N. |
| Abstract | A bridging fault simulator of CMOS VLSI circuits with timing information is described. It can detect delay as well as logic faults. A realistic resistive two-line bridging fault model is used. Mixed-mode bridging fault simulation without timing information is performed first to detect those faults that cause logic errors so as to reduce the fault set. Test vector selection, and mixed-mode timing simulation techniques are then used to speed up the simulation. Simulation results of some of the ISCAS 89 sequential benchmark circuits are given. 1 Introduction Bridging faults in VLSI circuits are caused by unintended connections between two (or more) normally unconnected signal lines. The unintended connections are usually caused by mask contamination, incomplete etching, or other physical failures and defects. Because the growing density of integration reduces the distance between lines and/or contacts, bridging faults are one of the most commonly encountered physical defects in VLSI cir... |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Mixed-mode Timing Simulation Accurate Cmos Bridging Fault Detection Unintended Connection Introduction Bridging Fault Vlsi Circuit Logic Fault Sequential Benchmark Circuit Mixed-mode Timing Simulation Technique Physical Failure Mask Contamination Cmos Vlsi Unconnected Signal Line Incomplete Etching Test Vector Selection Logic Error Mixed-mode Bridging Fault Simulation Vlsi Cir Bridging Fault Simulator Physical Defect Simulation Result |
| Content Type | Text |
