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Optimizing packet accesses for a domain specific language on network processors.
| Content Provider | CiteSeerX |
|---|---|
| Author | Liu, Tao Li, Xiao-Feng Liu, Lixia Wu, Chengyong Ju, Roy |
| Abstract | Abstract. Programming network processors remains a challenging task since their birth until recently when high-level programming environments for them are emerging. By employing domain specific languages for packet processing, the new environments try to hide hardware details from the programmers and enhance both the programmability of the systems and the portability of the ap-plications. A frequent issue for the new environments to be widely adopted is their relatively low achievable performance compared to low-level, hand-tuned programming. In this paper we present two techniques, Packet Access Combin-ing (PAC) and Compiler-Generated Packet Caching (CGPC), to optimize packet accesses, which are shown as the performance bottleneck in such new environments for packet processing applications. PAC merges multiple packet accesses into a single wider access; CGPC implements an automatic packet data caching mechanism without a hardware cache. Both techniques focus on reducing long memory latency and expensive memory traffic, and they also re-duce instruction counts significantly. We have implemented the proposed tech-niques in a high level programming environment for network processor named Shangri-La. Our evaluation with standard NPF benchmarks shows that for the evaluated applications the two techniques can reduce the memory traffic by 90 % and improve the packet throughput by 5.8 times, on average. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Network Processor Packet Access Domain Specific Language New Environment Hand-tuned Programming High-level Programming Environment Single Wider Access Frequent Issue Automatic Packet Data Low Achievable Performance Packet Throughput Packet Processing Standard Npf Benchmark Compiler-generated Packet Caching Long Memory Latency Memory Traffic Evaluated Application Expensive Memory Traffic Hardware Detail Performance Bottleneck High Level Packet Access Combin-ing Challenging Task Multiple Packet Instruction Count Hardware Cache Packet Processing Application |
| Content Type | Text |
| Resource Type | Article |
