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Computationally efficient multiplierless fir filters.
| Content Provider | CiteSeerX |
|---|---|
| Author | Coleman, Jeffrey O. |
| Abstract | Abstract — A two’s complement DSP signal can be multiplied by a fixed coefficient using an adder tree operating on input shifts cor-responding to nonzero coefficient bits. Alternatively, the signed bits of a canonical-signed-digit (CSD) coefficient representation specify an add/subtract network, with one third fewer terms re-quired on average. That well-known approach is generalized here to a radix-4 CSD system that turns out to save 36 % relative to conventional CSD in the FIR-filter application but at a per-filter overhead cost of six small-integer scaling operations that represent common subexpressions implicitly factored from the add/subtract network. The approach works for both direct-form and transposed-form filters and generalizes easily to other num-ber systems. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Efficient Multiplierless Fir Filter Add Subtract Network Input Shift Coefficient Bit Transposed-form Filter Common Subexpressions Coefficient Representation Num-ber System Well-known Approach Fir-filter Application Fixed Coefficient Adder Tree Complement Dsp Signal Conventional Csd Per-filter Overhead Cost Radix-4 Csd System Signed Bit |
| Content Type | Text |
