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Bandwidth-aware reconfigurable cache design with hybrid memory technologies.
| Content Provider | CiteSeerX |
|---|---|
| Author | Zhao, Jishen Xu, Cong Xie, Yuan |
| Abstract | Abstract—In chip-multiprocessor (CMP) designs, limited mem-ory bandwidth is a potential bottleneck of the system per-formance. New memory technologies, such as spin-transfer torque memory (STT-RAM), resistive memory (RRAM), and embedded DRAM (eDRAM), are promising on-chip memory solutions for CMPs. In this paper, we propose a bandwidth-aware reconfigurable cache hierarchy (BARCH) with hybrid memory technologies. BARCH consists of a hybrid cache hierarchy, a reconfiguration mechanism, and a statistical prediction engine. Our hybrid cache hierarchy chooses different memory technolo-gies to configure each level so that the bandwidth provided by the overall hierarchy is optimized. Furthermore, we present a reconfiguration mechanism to dynamically adapt the cache space of each level based on the predicted bandwidth demands of different applications, which is guaranteed by our prediction engine. We evaluate the system performance gain obtained by our method with a set of multithreaded and multiprogrammed ap-plications. Compared to traditional SRAM-based cache designs, our proposed design improves the system throughput by 58% and 14 % for multithreaded and multiprogrammed applications, respectively.1 I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Hybrid Memory Technology Bandwidth-aware Reconfigurable Cache Design Hybrid Cache Hierarchy Reconfiguration Mechanism Bandwidth Demand Resistive Memory Cache Space Different Application System Performance Gain Spin-transfer Torque Memory System Per-formance On-chip Memory Solution Different Memory Technolo-gies Overall Hierarchy Traditional Sram-based Cache Design Bandwidth-aware Reconfigurable Cache Hierarchy Prediction Engine Potential Bottleneck Limited Mem-ory Bandwidth New Memory Technology Statistical Prediction Engine |
| Content Type | Text |
