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Exception handling in microprocessors using assertion libraries fernando cortez sica dcc/ufmg – decom/ufop.
| Content Provider | CiteSeerX |
|---|---|
| Author | Carlos, Av. Antônio Junior, Claudionor N. Coelho Augusto, José Nacif, M. Foster, Harry Fernandes, Antônio Otávio |
| Abstract | In complex System-on-a-Chip (SoC) designs, designers often need to add new features into an original processor core, such as to extend the exception handling mechanism to consider exceptions in the remaining portion of the SoC design. We present in this paper a scalable architecture that can be used to add complex exception handling mechanisms in processor cores and how it can be used to extend the fixed set of exceptions found in microprocessor cores. This mechanism is based on the use of assertion libraries linked by an assertion processor to incorporate these new functionalities. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Exception Handling Scalable Architecture Original Processor Core Complex Exception Soc Design Microprocessor Core Processor Core Assertion Processor Complex System-on-a-chip New Functionality Assertion Library Fixed Set New Feature |
| Content Type | Text |
| Resource Type | Article |
