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Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs
| Content Provider | CiteSeerX |
|---|---|
| Author | Carvalho, Ewerson Calazans, Ney Moraes, Fernando |
| Description | Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the “design crisis ” (gap between silicon technology and actual SoC design capac-ity) and reduce the time to market. Important issues in MPSoC design are the communication infrastructure and task mapping. MPSoCs may employ NoCs to integrate multiple programmable processor cores, specialized memories, and other IPs in a scalable way. Applications running in MPSoCs execute a varying number of tasks simultaneously, and their number may exceed the available resources, requiring task mapping to be executed at run-time to meet real-time constraints. Most works in the lit-erature present static MPSoC mapping solutions. Static mapping defines a fixed placement and scheduling, not appropriate for dynamic workloads. Task migration has also been proposed for use in MPSoCs, with the goal to relocate tasks when performance bottlenecks are identi-fied. This work investigates the performance of mapping heuristics in NoC-based MPSoCs with dynamic workloads, targeting NoC congestion minimization, a key cost function to optimize the NoC performance. Here, tasks are mapped on the fly, according to communication requests and the load in the NoC links. Results show execution time and congestion reduction when congestion-aware mapping heuristics are employed. 1 |
| File Format | |
| Language | English |
| Publisher Institution | Proceedings of the 18 th IEEE/IFIP International Workshop on Rapid System Prototyping, 2007 |
| Access Restriction | Open |
| Subject Keyword | Noc-based Heterogeneous Mpsocs Noc Performance Static Mapping Multiple Programmable Processor Core Silicon Technology Communication Request Important Issue Mpsoc Design Actual Soc Design Capac-ity Task Migration Real-time Constraint Communication Infrastructure Congestion-aware Mapping Heuristic Noc Link Available Resource Key Cost Function Congestion Reduction Task Mapping Result Show Execution Time Noc Congestion Minimization Vlsi Design Noc-based Mpsocs Performance Bottleneck Dynamic Task Mapping Multiprocessor Systems-on-chip Fixed Placement Design Crisis Varying Number Dynamic Workload Specialized Memory Scalable Way |
| Content Type | Text |
| Resource Type | Article |
