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Reliability-aware design optimization for multiprocessor embedded systems.
| Content Provider | CiteSeerX |
|---|---|
| Author | Huang, Jia Blech, Jan Olaf Raabe, Andreas Buckl, Christian Knoll, Alois |
| Abstract | Abstract—This paper presents an approach for the reliability-aware design optimization of real-time systems on multi-processor platforms. The optimization is based on an extension of well accepted fault- and process-models. We combine utilization of hardware replication and software re-execution techniques to tolerate transient faults. A System Fault Tree (SFT) analysis is proposed, which computes the system-level reliability in presence of the hardware and software redundancy based on component failure probabilities. We integrate the SFT analysis with a Multi-Objective Evolutionary Algorithm (MOEA) based optimization process to perform efficient reliability-aware design space exploration. The solution resulting from our optimization contains the mapping of tasks to processing elements (PEs), the exact task and message sched-ule and the fault-tolerance policy assignment. The effectiveness of the approach is illustrated using several case studies. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Reliability-aware Design Optimization Multiprocessor Embedded System System Fault Tree Multi-objective Evolutionary Algorithm System-level Reliability Message Sched-ule Fault-tolerance Policy Assignment Software Redundancy Multi-processor Platform Software Re-execution Technique Several Case Study Real-time System Hardware Replication Optimization Process Sft Analysis Exact Task Efficient Reliability-aware Design Space Exploration Transient Fault Component Failure Probability |
| Content Type | Text |
