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A Coupled Multi-ALU Processing Node for a Highly Parallel Computer (1992)
| Content Provider | CiteSeerX |
|---|---|
| Author | Keckler, Stephen William |
| Abstract | By 1995, improvements in semiconductor technology will allow as many as four highperformance floating-point ALUs and several megabits of memory to reside on a single chip. Multiple arithmetic units can be organized into a single processor to exploit instruction-level parallelism. Processor Coupling is a mechanism for controlling multiple ALUs to exploit both instructionlevel and inter-thread parallelism. Processor Coupling employs both compile time and runtime scheduling. The compiler statically schedules individual threads to discover available intra-thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle by cycle basis, and several threads can be active concurrently. This thesis describes the architecture of a Processor Coupled node and evaluates parameters that affect performance. Processor Coupling is compared with a multiple ALU statical... |
| File Format | |
| Language | English |
| Publisher Date | 1992-01-01 |
| Publisher Institution | Massachusetts Inst |
| Access Restriction | Open |
| Subject Keyword | Processor Coupling Highly Parallel Computer Coupled Multi-alu Processing Node Inter-thread Parallelism Processor Coupled Node Mechanism Interleaf Thread Multiple Arithmetic Unit Runtime Scheduling Several Megabit Highperformance Floating-point Alus Available Intra-thread Instruction-level Parallelism High Alu Utilization Single Processor Compile Time Single Chip Several Thread Multiple Alus Individual Thread Cycle Basis Semiconductor Technology Instruction-level Parallelism Multiple Alu Statical |
| Content Type | Text |
| Resource Type | Technical Report |
