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Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages (1999)
| Content Provider | CiteSeerX |
|---|---|
| Author | Parhi, Keshab K. Speaker, Designated Sundararajan, Vijay |
| Abstract | A novel technique for incorporating the use of dual supply voltages for low power without performance degradation for gate level CMOS VLSI circuits is presented. A formal exact model is developed for the above problem and an efficient near-optimal heuristic is proposed. Power consumption savings up to 25% over and above the best known existing heuristics are demonstrated for combinational circuits in the ISCAS85 benchmark suite. 2 Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages October 9, 1998 Abstract Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply voltage for gates off the critical path it is possible to dramatically reduce power consumption in CMOS VLSI circuits without performance degradation. Interfacing gates operating under multiple supply voltages requires the use of level converters. Due to the non-negligible power c... |
| File Format | |
| Publisher Date | 1999-01-01 |
| Access Restriction | Open |
| Subject Keyword | Gate Level Cmos Vlsi Circuit Iscas85 Benchmark Suite Abstract Dynamic Power Cmos Gate Performance Degradation Level Converter Dual Supply Voltage Non-negligible Power Multiple Supply Voltage Cmos Vlsi Circuit Formal Exact Model High Supply Voltage Low Power Critical Path Efficient Near-optimal Heuristic Supply Voltage Novel Technique Combinational Circuit Power Consumption Low Supply Voltage |
| Content Type | Text |
