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An efficient vlsi design approach to reduce static power using variable body biasing 1.
| Content Provider | CiteSeerX |
|---|---|
| Author | Abindas P., K. Priyanga, Barani Coimbatore, Kaniyur |
| Abstract | In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance. existing transistors into two half size transistors like the stack approach. Then sleep transistors are added in parallel to one of the divided transistors. During sleep mode, sleep transistors are turned off and stacked transistors suppress leakage current while saving state. Area penalty is a significant matter for this approach since every transistor is replaced by three transistors. C. Sleepy Keeper Approach Sleepy keeper utilizes leakage feedback technique [5] (fig. 3). In this approach, a PMOS transistor is placed in parallel to the sleep transistor (S) and a NMOS transistor is placed in parallel to the sleep transistor (S'). The two transistors are driven by the output of the inverter. During sleep mode, sleep transistors are turned off and one of the transistors in parallel to the sleep transistors keep the connection with the appropriate power rail. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Sleep Transistor Static Power Consumption Efficient Vlsi Design Approach Variable Body Biasing Reduce Static Power Circuit Performance Sleep Mode New Method Power Density Nmos Transistor Sleepy Keeper Approach Sleepy Keeper Half Size Transistor Variable Body Biasing Technique Appropriate Power Rail Functional Integration Process Geometry Area Penalty Stack Approach Significant Matter Circuit Designer Area Requirement Technology Scaling Leakage Feedback Technique Cmos Vlsi Circuit Circuit Design Divided Transistor Pmos Transistor Static Power Result Static Power Consumption Design Area Clock Speed |
| Content Type | Text |
