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Effects of transmitter symbol clock jitter upon ground receiver performance (2010).
| Content Provider | CiteSeerX |
|---|---|
| Author | Srinivasan, Meera Tkacenko, Andre Lyubarev, Mark Estabrook, Polly |
| Abstract | In this article we characterize the effect of transmitter clock jitter upon receiver symbol synchronization performance. Using a sinusoidal model for the timing jitter, we evaluate the bit error rate (BER) degradation and cycle slip probabilities of receivers via analysis as well as simulation for uncoded offset quadrature-phase-shift-keying (OQPSK). We evaluate performance for two different symbol synchronization loops: the modified data transition tracking loop (M-DTTL) and the Gardner loop. The results are parameterized in terms of the timing jitter parameters (peak frequency jitter, time interval error, and cycle-to-cycle jitter) as well as symbol tracking loop parameters (loop damping factor, loop bandwidth). We present analytical expressions for BER degradation in the presence of sinusoidal timing jitter and compare results with those obtained via simulation, as well as past hardware tests of receivers. These results show that for both types of symbol synchronizers, peak BER degradation decreases as the loop damping factor increases, and that for underdamped tracking loops, the BER degradation peaks when the normalized jitter rate is approximately the same as the natural frequency of the loop transfer function. Simulated cycle-slip rates are also presented, showing the effects of varying loop bandwidths and damping factors. Finally, we illustrate how BER degradation can be characterized in terms of jitter time interval error and cycle-to-cycle jitter, providing predictive capabilities for receiver performance and guidelines for the specification of transmitter clock requirements. I. |
| File Format | |
| Publisher Date | 2010-01-01 |
| Access Restriction | Open |
| Subject Keyword | Ber Degradation Cycle-to-cycle Jitter Time Interval Error Data Transition Loop Transfer Function Bit Error Rate Predictive Capability Peak Frequency Jitter Jitter Time Interval Error Loop Bandwidth Compare Result Factor Increase Past Hardware Test Natural Frequency Timing Jitter Gardner Loop Cycle Slip Probability Receiver Symbol Synchronization Performance Ber Degradation Peak Timing Jitter Parameter Transmitter Clock Requirement Normalized Jitter Rate Loop Parameter Receiver Performance Sinusoidal Timing Jitter Symbol Synchronizer Sinusoidal Model Present Analytical Expression Simulated Cycle-slip Rate Different Symbol Synchronization Loop Peak Ber Degradation Transmitter Clock Jitter |
| Content Type | Text |
| Resource Type | Article |
