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RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors (1997)
| Content Provider | CiteSeerX |
|---|---|
| Author | Ranganathan, Parthasarathy Adve, Sarita V. Pai, Vijay S. |
| Abstract | This paper describes RSIM -- the Rice Simulator for ILP Multiprocessors -- Version 1.0. RSIM simulates shared-memory multiprocessors (and uniprocessors) built from processors that aggressively exploit instruction-level parallelism (ILP). RSIM is execution-driven and models state-of-the-art ILP processors, an aggressive memory system, and a multiprocessor coherence protocol and interconnect, including contention at all resources. Although originally designed as a research tool, RSIM is also being used successfully in both undergraduate and graduate computer architecture courses at Rice University. RSIM version 1.0 is publicly available. 1 Introduction This paper describes RSIM -- the Rice Simulator for ILP Multiprocessors -- Version 1.0. RSIM is primarily designed to study shared-memory multiprocessor architectures built from processors that aggressively exploit instruction-level parallelism (ILP). It models state-of-the-art ILP processors, an aggressive memory system, and a multipr... |
| File Format | |
| Publisher Date | 1997-01-01 |
| Access Restriction | Open |
| Subject Keyword | Model State-of-the-art Ilp Processor Rice Simulator Rsim Version Ilp-based Shared-memory Multiprocessor Rice University Shared-memory Multiprocessor Execution-driven Simulator Shared-memory Multiprocessor Architecture Aggressive Memory System Research Tool Instruction-level Parallelism Graduate Computer Architecture Course Multiprocessor Coherence Protocol Ilp Multiprocessor Version |
| Content Type | Text |
| Resource Type | Article |
