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A power-aware mapping approach to map ip cores onto nocs under bandwidth and latency constraints (2010).
| Content Provider | CiteSeerX |
|---|---|
| Author | Wang, Xiaohang Yang, Mei Jiang, Yingtao Liu, Peng |
| Abstract | In this article, we investigate the Intellectual Property (IP) mapping problem that maps a given set of IP cores onto the tiles of a mesh-based Network-on-Chip (NoC) architecture such that the power consumption due to intercore communications is minimized. This IP mapping problem is considered under both bandwidth and latency constraints as imposed by the applications and the on-chip network infrastructure. By examining various applications ’ communication characteristics extracted from their respective communication trace graphs, two distinguishable connectivity templates are realized: the graphs with tightly coupled vertices and those with distributed vertices. These two templates are formally defined in this article, and different mapping heuristics are subsequently developed to map them. In general, tightly coupled vertices are mapped onto tiles that are physically close to each other while the distributed vertices are mapped following a graph partition scheme. Experimental results on both random and multimedia benchmarks have confirmed that the proposed template-based mapping algorithm achieves an average of 15 % power savings as compared with MOCA, a fast greedy-based mapping algorithm. Compared with a branch-andbound–based mapping algorithm, which produces near optimal results but incurs an extremely high computation cost, the proposed algorithm, due to its polynomial runtime complexity, can generate |
| File Format | |
| Publisher Date | 2010-01-01 |
| Access Restriction | Open |
| Subject Keyword | Latency Constraint Map Ip Core Power-aware Mapping Approach Distributed Vertex Multimedia Benchmark Ip Mapping Problem Intellectual Property Different Mapping Heuristic Polynomial Runtime Complexity Various Application Communication Characteristic Optimal Result Mesh-based Network-on-chip Mapping Problem Graph Partition Scheme Distinguishable Connectivity Template High Computation Cost Ip Core On-chip Network Infrastructure Power Consumption Power Saving Mapping Algorithm Fast Greedy-based Mapping Algorithm Template-based Mapping Algorithm Respective Communication Trace Graph Experimental Result |
| Content Type | Text |
