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Power-aware run-time incremental mapping for 3-d networks-on-chip.
| Content Provider | CiteSeerX |
|---|---|
| Author | Wang, Xiaohang Palesi, Maurizio Yang, Mei Jiang, Yingtao Huang, Michael C. Liu, Peng |
| Abstract | Abstract. 3-D Networks-on-Chip (NoCs) emerge as a powerful solution to address both the interconnection and design complexity problems facing future Systems-on-Chip (SoCs). Effective run-time application mapping on a 3-D NoC-based Multiprocessor Systems-on-Chip (MPSoC) can be quite challenging, largely due to the fact that the arrival order and task graphs of the target applications are not known a priori. This paper presents a power-aware run-time incremental mapping algorithm for 3-D NoCs that aims to minimize the communication power for each incoming application as well as reduce the impact of the mapped applications on future applications that are yet to be mapped. In this algorithm, if the vertical links are found to be shorter and provide higher communication bandwidth than horizontal links, more communications will be mapped to vertical links to reduce delay and power consumption. Extensive experiments have been conducted to evaluate the performance of the proposed algorithm and the results are compared with those obtained from the optimal mapping algorithm (branch-and-bound), a random mapping and a simple heuristic. When mapping a single application, the proposed algorithm is four orders of magnitude faster than the branch-andbound algorithm at a small degradation of mapping quality. When mapping multiple applications incrementally, our algorithm can save 50% communication power compared to the random mapping and 20% communication power compared to the simple heuristic. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | 3-d Networks-on-chip Communication Power Power-aware Run-time Incremental Mapping Random Mapping Vertical Link Simple Heuristic Mapped Application Extensive Experiment Branch-andbound Algorithm Optimal Mapping Algorithm 3-d Noc-based Multiprocessor Systems-on-chip Power Consumption Arrival Order Effective Run-time Application Mapping Horizontal Link Task Graph Powerful Solution Small Degradation Power-aware Run-time Incremental Mapping Algorithm 3-d Noc Single Application Target Application Communication Bandwidth Multiple Application Future Application |
| Content Type | Text |
| Resource Type | Article |
