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Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric.
| Content Provider | CiteSeerX |
|---|---|
| Author | Dousti, Mohammad Javad Pedram, Massoud |
| Abstract | Abstract — Quantum computers are exponentially faster than their classical counterparts in terms of solving some specific, but important problems. The biggest challenge in realizing a quantum computing system is the environmental noise. One way to decrease the effect of noise (and hence, reduce the overhead of building fault tolerant quantum circuits) is to reduce the latency of the quantum circuit that runs on a quantum circuit. In this paper, a novel algorithm is presented for scheduling, placement, and routing of a quantum algorithm, which is to be realized on a target quantum circuit fabric technology. This algorithm, and the accompanying software tool, advances state-of-the-art in quantum CAD methodologies and methods while considering key characteristics and constraints of the ion-trap quantum circuit fabric. Experimental results show that the presented tool improves results of the previous tool by about 41%. Keywords- quantum computing; scheduling; routing; placement; ion-trap technology; CAD tool I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Quantum Circuit Ion-trap Circuit Fabric Quantum Cad Methodology Building Fault Tolerant Quantum Circuit Target Quantum Circuit Fabric Technology Environmental Noise Software Tool Quantum Algorithm Ion-trap Quantum Circuit Fabric Abstract Quantum Computer Important Problem Ion-trap Technology Key Characteristic Classical Counterpart Presented Tool Experimental Result Novel Algorithm Cad Tool Previous Tool |
| Content Type | Text |
