Counterflow pipeline processor architecture (1994).

Content Provider	CiteSeerX
Author	Sproull, Robert Sutherland, Ivan E. Molnar, Charles E.
Abstract	: The counterflow pipeline processor architecture (cfpp) is a proposal for a family of microarchitectures for risc processors. The architecture derives its name from its fundamental feature, namely that instructions and results flow in opposite directions within a pipeline and interact as they pass. The architecture seeks geometric regularity in processor chip layout, purely local control to avoid performance limitations of complex global pipeline stall signals, and simplicity that might lead to provably correct processor designs. Moreover, cfpp designs allow asynchronous implementations, in contrast to conventional pipeline designs where the synchronization required for operand forwarding makes asynchronous designs unattractive. This paper presents the cfpp architecture and a proposal for an asynchronous implementation. Detailed performance simulations of a complete processor design are not yet available. Keywords: processor design, risc architecture, micropipelines, fifo, asynchronou...
File Format	PDF
Publisher Date	1994-01-01
Access Restriction	Open
Subject Keyword	Counterflow Pipeline Processor Architecture Processor Design Asynchronous Implementation Risc Architecture Cfpp Design Complex Global Pipeline Stall Signal Conventional Pipeline Design Asynchronous Design Fundamental Feature Operand Forwarding Risc Processor Detailed Performance Simulation Opposite Direction Local Control Geometric Regularity Processor Chip Layout Performance Limitation Complete Processor Design Cfpp Architecture
Content Type	Text
Resource Type	Article