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Adiabatic Switching and Power Dissipation of Dynamic Resonant Tunneling Device Logic Circuits (1998)
| Content Provider | CiteSeerX |
|---|---|
| Author | Pacha, Christian Glösekötter, Peter Goser, Karl |
| Description | Dynamic power dissipation is an important aspect of resonant tunneling device circuit design, especially if clock frequencies beyond 1 GHz are intended. In this paper we investigate the different sources of power dissipation of a dynamic resonant tunneling device logic family. Due to the self-latching behavior of the gates and the bitlevel pipelined circuit style an adiabatic clocking scheme is ideally suited to reduce the dynamic switching energy. Extrapolations for laterally scaled resonant tunneling devices predict a total power dissipation below 20 W per gate at 5 GHz for a minimum feature size of 200 nm and a peak current density of j P = 10 kA=cm 2 . Compared to a non-adiabatic operation this is a reduction of the switching energy by about one order of magnitude. 1. Introduction Resonant tunneling device circuits composed of a dynamic latch and an embedded logic input stage play an important role as precursors for future nano-scale circuits with reduced complexity. Recently, ... |
| File Format | |
| Language | English |
| Publisher Date | 1998-01-01 |
| Publisher Institution | In Proceedings of the 3rd Workshop on Innovative Circuits and Systems for Nanoelectronics. TU Munich, Lehrstuhl für Technische Elektronik |
| Access Restriction | Open |
| Subject Keyword | Clock Frequency Embedded Logic Input Stage Circuit Style Different Source Dynamic Resonant Introduction Resonant Tunneling Device Circuit Important Role Future Nano-scale Circuit Dynamic Switching Energy Important Aspect Adiabatic Switching Self-latching Behavior Total Power Dissipation Dynamic Power Dissipation Peak Current Density Device Circuit Design Reduced Complexity Minimum Feature Size Non-adiabatic Operation Power Dissipation Adiabatic Clocking Scheme Dynamic Latch |
| Content Type | Text |
| Resource Type | Article |
