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Removing User Specified False Paths from Timing Graphs (2000)
| Content Provider | CiteSeerX |
|---|---|
| Author | Blaauw, David Rajendran, P. Das, Abhijit |
| Description | We present a new method for removing user-specified false subgraphs from timing analysis and circuit optimization. Given a timing graph and a list of specified false paths, false subpaths, or false subgraphs, we generate a new timing graph in which all specified false paths are removed using a process of node splitting and edge removal. We present the necessary and sufficient condition for splitting a node, and show that the number of nodes that must be added to the timing graph is linear with the size of the false path specification. We also present an algorithm for finding the minimum set of nodes that must be split. Since this algorithm requires exponential run time for false subpaths and false subgraphs, we present a heuristic splitting approach which has linear worst-case run time, and where the number of added nodes is linear with the size of the false path specification. The heuristic approach was implemented and results are given for large industrial circuits. 1. in Proc. DAC |
| File Format | |
| Language | English |
| Publisher Date | 2000-01-01 |
| Access Restriction | Open |
| Subject Keyword | Node Splitting Heuristic Approach Sufficient Condition Specified False Path False Subpaths User-specified False Subgraphs Heuristic Splitting Approach False Subgraphs Timing Graph False Path False Path Specification Worst-case Run Time Exponential Run Time Circuit Optimization User Specified False Path Large Industrial Circuit Minimum Set Added Node New Timing Graph New Method Edge Removal |
| Content Type | Text |
| Resource Type | Article |
