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3.3 Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device
| Content Provider | CiteSeerX |
|---|---|
| Author | Chuang, Ching-Te Joshi, Rajiv V. Das, Koushik K. Kim, Keunwoo |
| Abstract | Leakage power for extremely scaled (L eff = 25 nm) doublegate devices is examined. Numerical two-dimensional simulation results for double-gate CMOS device/circuit power are presented from physics principle, identifying that doublegate technology is an ideal candidate for low-power applications. Unique double-gate device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design tradeoffs for double-gate CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for double-gate device are analyzed considering state dependency, showing that leakage current is reduced by a factor of over 10X, compared with conventional bulk-Si counterpart. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Doublegate Technology Conventional Bulk-si Counterpart Numerical Two-dimensional Simulation Result Leakage Power Doublegate Device High-performance Application Design Tradeoff Unique Double-gate Device Feature Dynamic Circuit Double-gate Cmos Device Circuit Power Optimal Low-leakage Device Design State Dependency Double-gate Cmos Power Total Power Consumption Double-gate Device Ideal Candidate Physic Principle Gate-gate Coupling |
| Content Type | Text |
