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Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model. Design Automation (1994)
| Content Provider | CiteSeerX |
|---|---|
| Author | Kahng, Andrew B. Muddu, Sudhakar |
| Description | The traditional analysis of signal delay in a transmission line begins with a lossless LC representation, which yields a wave equation governing the system response; 2-port parameters are typically derived and the solution is obtained in the transform domain. In this paper, we begin with a distributed RC line model of the interconnect and analytically solve the resulting di usion equation for the voltage response. A new closed form expression for voltage response is obtained by incorporating appropriate boundary conditions for interconnect delay analysis. Calculations of 50 % and 90 % delay times for various cases of interest (e.g., open-ended RC line) give substantially di erent estimates from those commonly cited in the literature, thus suggesting revised delay estimation methodologies and intuitions for the design of VLSI interconnects. The discussion furthermore provides a unifying treatment of the past three decades of RC interconnect delay analyses. 1 |
| File Format | |
| Language | English |
| Publisher Date | 1994-01-01 |
| Publisher Institution | 31st Conference on, 0:563–569 |
| Access Restriction | Open |
| Subject Keyword | Delay Estimation Methodology Rc Interconnect Delay Analysis Voltage Response Transmission Line Appropriate Boundary Condition Traditional Analysis Open-ended Rc Line Diffusion Equation Model Various Case Design Automation Di Usion Equation Delay Analysis Vlsi Interconnects Wave Equation Signal Delay New Closed Form Expression Transform Domain Interconnect Delay Analysis System Response Unifying Treatment 2-port Parameter Delay Time Lossless Lc Representation Vlsi Interconnection Distributed Rc Line Model Di Erent Estimate |
| Content Type | Text |
| Resource Type | Article |
