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22.1 a 125µw, fully scalable mpeg-2 and h.264/avc video decoder for mobile applications.
| Content Provider | CiteSeerX |
|---|---|
| Author | Liu, Tsu-Ming Lin, Ting-An Wang, Sheng-Zen Lee, Wen-Ping Hou, Kang-Cheng Yang, Jiun-Yan Lee, Chen-Yi |
| Abstract | decoder is fabricated in a 0.18µm 1P6M CMOS technology with an area of 15.21mm 2. This chip contains 19.2kb and 3.55kb of embedded SRAM for storing neighboring pixels and control tags, and adopts two 4MB SDRAMs for further system integration. It operates at a power-level that is about one order of magnitude less than comparable decoders. This savings in power consumption was attained by means of both throughput and bandwidth improvements while incorporating scalable features. For mobile applications, MPEG-2 and H.264/AVC video decoding of QCIF sequences at 15 frames per second is achieved at a clock frequency of 1.15MHz and requires 108µW and 125µW, respectively, at 1V supply voltage. Moreover, CIF, D1 and HD resolutions are also supported. The chip features are summarized in Fig. 22.1.1. The advent of H.264/AVC provides high compression ratio, but, there is no backward compatibility to the prevalent MPEG-x and |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Mobile Application Avc Video Decoder Fully Scalable Mpeg-2 Neighboring Pixel Bandwidth Improvement Clock Frequency Scalable Feature Control Tag Backward Compatibility Hd Resolution Prevalent Mpeg-x Power Consumption Qcif Sequence Supply Voltage Cmos Technology Comparable Decoder Chip Feature System Integration Avc Video Decoding High Compression Ratio |
| Content Type | Text |
