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Polyhedral-based data reuse optimization for configurable computing (2013)
| Content Provider | CiteSeerX |
|---|---|
| Author | Pouchet, Louis-Noël Zhang, Peng Cong, Jason |
| Description | Many applications, such as medical imaging, generate intensive data traffic between the FPGA and off-chip memory. Significant improvements in the execution time can be achieved with effective utilization of on-chip (scratchpad) memories, associated with careful software-based data reuse and communication scheduling techniques. We present a fully automated C-to-FPGA framework to address this problem. Our framework effectively implements data reuse through aggressive loop transformation-based program restructuring. In addition, our proposed framework automatically implements critical optimizations for performance such as task-level parallelization, loop pipelining, and data prefetching. We leverage the power and expressiveness of the polyhedral compilation model to develop a multi-objective optimization system for off-chip communications management. Our technique can satisfy hardware resource constraints (scratchpad size) while still aggressively exploiting data reuse. Our approach can also be used to reduce the on-chip buffer size subject to bandwidth constraint. We also implement a fast design space exploration technique for effective optimization of program performance using the Xilinx high-level synthesis tool. In FPGA |
| File Format | |
| Language | English |
| Publisher Date | 2013-01-01 |
| Access Restriction | Open |
| Subject Keyword | Hardware Resource Constraint Multi-objective Optimization System Xilinx High-level Synthesis Tool Intensive Data Traffic Aggressive Loop Transformation-based Program Restructuring Polyhedral-based Data Reuse Optimization Critical Optimization Medical Imaging Loop Pipelining Off-chip Communication Management Execution Time Many Application Task-level Parallelization Scratchpad Size Polyhedral Compilation Model Program Performance Careful Software-based Data Reuse Effective Utilization On-chip Buffer Size Subject Fast Design Space Exploration Technique Significant Improvement C-to-fpga Framework Effective Optimization Off-chip Memory Data Reuse Configurable Computing |
| Content Type | Text |
| Resource Type | Article |
