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Fast Hardware Compilation of Behaviors into an FPGA-Based Dynamic Reconfigurable Computing System (1999)
| Content Provider | CiteSeerX |
|---|---|
| Author | Cardoso, João M. P. Neto, Horácio C. |
| Description | This report presents new techniques for architecture and performance driven compilation of software programs into reconfigware (reconfigurable hardware). These new techniques effectively improve on the complex resource sharing approaches typical of High-Level Synthesis algorithms, which are efficient for layout flexible ASICs but are clearly not adequate for reconfigurable devices with pre-defined architectures because of control overhead and complex routing requirements. The compilation flow takes advantage of a specialized library of circuit-generators and only resorts to logic synthesis for the generation of the data-path's control unit. It integrates temporal partitioning algorithms able to exploit efficiently the concept of "virtual hardware" by time-multiplexing the FPGA resources. The algorithms under development are being integrated onto our hardware compiler that accepts behaviors previously compiled to Java Bytecodes. A series of experiments has been performed using a numb... |
| File Format | |
| Language | English |
| Publisher | Society Press |
| Publisher Date | 1999-01-01 |
| Publisher Institution | Proc. of the XII Symposium on Integrated Circuits and Systems Design (SBCCI’99), (Co -)Sponsored by the Brazilian Computer Society and the IFIP WG 10.5 |
| Access Restriction | Open |
| Subject Keyword | Java Bytecodes Complex Resource Fast Hardware Compilation Software Program Compilation Flow Fpga-based Dynamic Reconfigurable Computing System Layout Flexible Asics Specialized Library Reconfigurable Device Virtual Hardware Reconfigurable Hardware Hardware Compiler Complex Routing Requirement Pre-defined Architecture New Technique Fpga Resource High-level Synthesis Algorithm |
| Content Type | Text |
| Resource Type | Article |
